View QL12X16B_280607.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

QL12X16B pASIC(R) 1 Family Very-High-Speed CMOS FPGA
Rev C pASIC HIGHLIGHTS Very High Speed - ViaLink(R) metal-to-metal programmable-via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns. High Usable Density - A 12-by-16 array of 192 logic cells provides 2,000 usable ASIC gates (4,000 PLD gates) in 68-pin and 84-pin PLCC, 84-pin CPGA and 100-pin TQFP packages. Low-Power, High-Output Drive - Standby current typically 2 mA. A 16-bit counter operating at 100 MHz consumes less than 50 mA. Minimum IOL of 12 mA and IOH of 8 mA Low-Cost, Easy-to-Use Design Tools - Designs entered and simulated using QuickLogic's new QuickWorks(R) development environment, or with third-party CAE tools including Viewlogic, Synopsys, Mentor, Cadence and Veribest. Fast, fully automatic place and route on PC and workstation platforms using QuickLogic software.
...2,000 usable ASIC gates, 88 I/O pins
4
pASIC 1
QL12X16B Block Diagram
192 Logic Cells
= Up to 80 prog. I/O cells, 6 Input high-drive cells, 2 Input/Clk (high-drive) cells
4-13
QL12X16B
PRODUCT SUMMARY The QL12X16B is a member of the pASIC 1 Family of very-high-speed CMOS user-programmable ASIC devices. The 192 logic cell fieldprogrammable gate array (FPGA) offers 2,000 usable ASIC gates (4,000 usable PLD gates) of high-performance general-purpose logic in a wide variety of package configurations. Low-impedance, metal-to-metal, ViaLink interconnect technology provides nonvolatile custom logic capable of operating above 150 MHz. Logic cell delays under 2 ns, combined with input delays of under 1.5 ns and output delays under 3 ns, permit high-density programmable devices to be used with today's fastest microprocessors and DSPs. Designs can be entered using QuickLogic's QuickWorks Toolkit or most populart third-party CAE tools. QuickWorks combines Verilog/VHDL design entry and simulation tools with device-specific place & route and programming software. Ample on-chip routing channels allow fast, fully automatic place and route of designs using up to 100% of the logic and I/O cells, while maintaining fixed pin-outs. FEATURES Total of 88 I/O pins - 80 Bidirectional Input/Output pins - 6 Dedicated Input/High-Drive pins - 2 Clock/Dedicated input pins with fanout-independent, low-skew clock networks Input + logic cell + output delays under 6 ns Chip-to-chip operating frequencies up to 110 MHz Internal state machine frequencies up to 150 MHz Clock skew < 0.5 ns Input hysteresis provides high noise immunity Built-in scan path permits 100% factory testing of logic and I/O cells and functional testing with Automatic Test Vector Generation (ATVG) software after programming Available in 68-pin and 84-pin PLCC, 84-pin CPGA and 100-pin TQFP packages 68-pin PLCC compatible with QL8x12B 84-pin PLCC compatible with QL16x24B 100-pin TQFP compatible with QL8x12B and QL16x24B 0.65 CMOS process with ViaLink programming technology
4-14
QL12X16B
Pinout Diagram 68-pin PLCC
4
pASIC 1
Pinout Diagram 84-pin PLCC
Pins identified I/SCLK, SM, SO and SI are used during scan path testing operation.
4-15
QL12X16B
Pinout Diagram 84-pin CPGA
M
CPGA 84 Function/Connector Pin Table
PIN B10 B9 A10 A9 B8 A8 A7 C7 A6 B7 C6 B6 B5 C5 A5 A4 B4 A3 A2 B3 A1 FUNC IO IO IO IO IO IO IO GND IO I/(SCLK) I/CLK/(SM) I(P) I VCC IO IO IO IO IO IO IO PIN B2 C2 B1 C1 D2 D1 E1 E3 E2 F1 F2 F3 G1 G3 G2 H1 H2 J1 K1 J2 L1 FUNC IO IO IO IO IO IO IO GND IO IO IO IO IO VCC IO IO IO IO IO IO IO PIN K2 K3 L2 L3 K4 L4 L5 J5 L6 K5 J6 K6 K7 J7 L7 L8 K8 L9 L10 K9 L11 FUNC IO IO IO IO IO IO IO GND IO I/(SI) I/CLK I I/(SO) VCC IO IO IO IO IO IO IO PIN K10 J10 K11 J11 H10 H11 G11 G9 G10 F11 F10 F9 E11 E9 E10 D11 D10 C11 B11 C10 A11 FUNC IO IO IO IO IO IO IO GND IO IO IO IO IO VCC IO IO IO IO IO IO IO
4-16
QL12X16B
Pinout Diagram 100-pin TQFP
4
pASIC 1
4-17
QL12X16B
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ................................. -0.5 to 7.0V Input Voltage ....................... -0.5 to VCC +0.5V ESD Pad Protection .................................. 2000V DC Input Current...................................... 20 mA Latch-up Immunity................................. 200 mA Storage Temperature .......-65C to + 150C Lead Temperature ...................................300C
OPERATING RANGE
Symbol VCC TA TC K Parameter Supply Voltage Ambient Temperature Case Temperature -X Speed Grade Delay Factor -0 Speed Grade -1 Speed Grade -2 Speed Grade Military Min Max 4.5 5.5 -55 125 0.39 0.39 1.82 1.56 Industrial Min Max 4.5 5.5 -40 85 0.4 0.4 0.4 0.4 2.75 1.67 1.43 1.35 Commercial Min Max 4.75 5.25 0 70 0.46 0.46 0.46 0.46 2.55 1.55 1.33 1.25 Unit V C C
DC CHARACTERISTICS over operating range
Symbol VIH VIL VOH VOL II IOZ CI IOS ICC Parameter Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Input Leakage Current 3-State Output Leakage Current Input Capacitance [1] Output Short Circuit Current [2] D.C. Supply Current [3] Conditions Min 2.0 3.7 2.4 VCC-0.1 0.4 0.1 10 10 10 -80 140 10 Max 0.8 IOH = -4 mA IOH = -8 mA IOH = -10 A IOL = 12 mA* IOL = 10 A VI = VCC or GND VI = VCC or GND VO = GND VO = VCC VI, VIO = VCC or GND Unit V V V V V V V A A pF mA mA mA
-10 -10 -10 30
*IOL = 12 mA for commercial range only. IOL = 8 mA for the industrial and military ranges. Notes: [1] [2] [3] [4] Capacitance is sample tested only. CI = 20 pF max on I/(SI). Only one output at a time. Duration should not exceed 30 seconds. Commercial temperature grade only. Maximum Icc for industrial grade is 15mA and for military grade is 20 mA. For AC conditions use the formula described in the Section 9 -- Power vs Operating Frequency. Stated timing for worst case Propagation Delay over process variation at VCC = 5.0V and TA = 25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. These limits are derived from a representative selection of the slowest paths through the pASIC logic cell including net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design.
[5]
4-18
QL12X16B
AC CHARACTERISTICS at VCC = 5V, TA = 25C (K = 1.00) Logic Cell
Symbol tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW Parameter Combinatorial Delay [5] Setup Time [5] Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width 1 1.7 2.1 0.0 1.0 2.0 2.0 1.7 1.5 1.9 1.8 Propagation Delays (ns) Fanout 2 3 4 2.2 2.6 3.2 2.1 2.1 2.1 0.0 0.0 0.0 1.5 1.9 2.5 2.0 2.0 2.0 2.0 2.0 2.0 2.1 2.6 3.2 1.9 2.2 2.7 1.9 1.9 1.9 1.8 1.8 1.8
8 5.2 2.1 0.0 4.6 2.0 2.0 5.2 4.3 1.9 1.8
Input Cells
Symbol tIN tINI tIO tGCK tGCKHI tGCKLO Parameter High Drive Input Delay [6] High Drive Input, Inverting Delay [6] Input Delay (bidirectional pad) Clock Buffer Delay [7] Clock Buffer Min High [7] Clock Buffer Min Low [7] 1 2.4 2.5 1.4 2.7 2.0 2.0 Propagation Delays (ns) [4] 2 2.5 2.6 1.9 2.8 2.0 2.0 3 2.6 2.7 2.2 2.8 2.0 2.0 4 2.7 2.8 2.8 2.9 2.0 2.0 6 3.0 3.1 3.7 2.9 2.0 2.0 8 3.3 3.4 4.6 3.0 2.0 2.0
4
pASIC 1
Output Cell
Symbol tOUTLH tOUTHL tPZH tPZL tPHZ tPLZ Notes: [6] [7] [8] See High Drive Buffer Table for more information. Clock buffer fanout refers to the maximum number of flip flops per half column. The number of half columns used does not affect clock buffer delay. tPHZ 1K The following loads are used for tPXZ: 5 pF
1K tPLZ 5 pF
Parameter Output Delay Low to High Output Delay High to Low Output Delay Tri-state to High Output Delay Tri-state to Low Output Delay High to Tri-state [8] Output Delay Low to Tri-state [8] 30 2.7 2.8 4.0 3.6 2.9 3.3
Propagation Delays (ns) [4] Output Load Capacitance (pF) 50 75 100 3.4 4.2 5.0 3.7 4.7 5.6 4.9 6.1 7.3 4.2 5.0 5.8
150 6.7 7.6 9.7 7.3
4-19
QL12X16B
High Drive Buffer
Symbol Parameter Clock Drivers Wired Together 1 2 3 4 1 2 3 4 Propagation Delays (ns) [4] Fanout 12 24 48 72 96 4.5 5.4 3.9 5.6 4.5 5.3 6.3 4.6 5.3 4.7 5.6 4.0 5.8 4.6 5.5 6.4 4.8 5.5
tIN
High Drive Input Delay
tINI
High Drive Input, Inverting Delay
AC Performance Propagation delays depend on routing, fanout, load capacitance, supply voltage, junction temperature, and process variation. The AC Characteristics are a design guide to provide initial timing estimates at nominal conditions. Worst case estimates are obtained when nominal propagation delays are multiplied by the appropriate Delay Factor, K, as specified in the Delay Factor table (Operating Range). The effects of voltage and temperature variation are illustrated in the graphs on page 4-47, K Factor versus Voltage and Temperature. The pASIC Development Tools incorporate data sheet AC Characteristics into the QDIF database for pre-place-and-route timing analysis. The SpDE Delay Modeler extracts specific timing parameters for precise path analysis or simulation results following place and route.
ORDERING INFORMATION
QL 12x16B - 1 PF100 C
QuickLogic pASIC device prefix Operating Range C = Commercial I = Industrial M = Military M/883C = MIL-STD-883
pASIC device part number B = 0.65 micron CMOS
Speed Grade X = quick 0 = fast 1 = faster 2 = fastest
Package Code PL68 = 68-pin PLCC PL84 = 84-pin PLCC CG84 = 84-pin CPGA PF100 = 100-pin TQFP
4-20

▲Up To Search▲

Price & Availability of QL12X16B

	To Download QL12X16B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .